macros.h 98 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952
  1. /*****************************************************************************
  2. * macros.h: msa macros
  3. *****************************************************************************
  4. * Copyright (C) 2015-2018 x264 project
  5. *
  6. * Authors: Rishikesh More <rishikesh.more@imgtec.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
  21. *
  22. * This program is also available under a commercial proprietary license.
  23. * For more information, contact us at licensing@x264.com.
  24. *****************************************************************************/
  25. #ifndef X264_MIPS_MACROS_H
  26. #define X264_MIPS_MACROS_H
  27. #include <stdint.h>
  28. #include <msa.h>
  29. #define LD_B( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
  30. #define LD_UB( ... ) LD_B( v16u8, __VA_ARGS__ )
  31. #define LD_SB( ... ) LD_B( v16i8, __VA_ARGS__ )
  32. #define LD_H( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
  33. #define LD_SH( ... ) LD_H( v8i16, __VA_ARGS__ )
  34. #define LD_W( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
  35. #define LD_SW( ... ) LD_W( v4i32, __VA_ARGS__ )
  36. #define ST_B( RTYPE, in, p_dst ) *( ( RTYPE * )( p_dst ) ) = ( in )
  37. #define ST_UB( ... ) ST_B( v16u8, __VA_ARGS__ )
  38. #define ST_SB( ... ) ST_B( v16i8, __VA_ARGS__ )
  39. #define ST_H( RTYPE, in, p_dst ) *( ( RTYPE * )( p_dst ) ) = ( in )
  40. #define ST_UH( ... ) ST_H( v8u16, __VA_ARGS__ )
  41. #define ST_SH( ... ) ST_H( v8i16, __VA_ARGS__ )
  42. #if ( __mips_isa_rev >= 6 )
  43. #define LH( p_src ) \
  44. ( { \
  45. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  46. uint16_t u_val_h_m; \
  47. \
  48. asm volatile ( \
  49. "lh %[u_val_h_m], %[p_src_m] \n\t" \
  50. \
  51. : [u_val_h_m] "=r" ( u_val_h_m ) \
  52. : [p_src_m] "m" ( *p_src_m ) \
  53. ); \
  54. \
  55. u_val_h_m; \
  56. } )
  57. #define LW( p_src ) \
  58. ( { \
  59. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  60. uint32_t u_val_w_m; \
  61. \
  62. asm volatile ( \
  63. "lw %[u_val_w_m], %[p_src_m] \n\t" \
  64. \
  65. : [u_val_w_m] "=r" ( u_val_w_m ) \
  66. : [p_src_m] "m" ( *p_src_m ) \
  67. ); \
  68. \
  69. u_val_w_m; \
  70. } )
  71. #if ( __mips == 64 )
  72. #define LD( p_src ) \
  73. ( { \
  74. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  75. uint64_t u_val_d_m = 0; \
  76. \
  77. asm volatile ( \
  78. "ld %[u_val_d_m], %[p_src_m] \n\t" \
  79. \
  80. : [u_val_d_m] "=r" ( u_val_d_m ) \
  81. : [p_src_m] "m" ( *p_src_m ) \
  82. ); \
  83. \
  84. u_val_d_m; \
  85. } )
  86. #else // !( __mips == 64 )
  87. #define LD( p_src ) \
  88. ( { \
  89. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  90. uint32_t u_val0_m, u_val1_m; \
  91. uint64_t u_val_d_m = 0; \
  92. \
  93. u_val0_m = LW( p_src_m ); \
  94. u_val1_m = LW( p_src_m + 4 ); \
  95. \
  96. u_val_d_m = ( uint64_t ) ( u_val1_m ); \
  97. u_val_d_m = ( uint64_t ) ( ( u_val_d_m << 32 ) & \
  98. 0xFFFFFFFF00000000 ); \
  99. u_val_d_m = ( uint64_t ) ( u_val_d_m | ( uint64_t ) u_val0_m ); \
  100. \
  101. u_val_d_m; \
  102. } )
  103. #endif // ( __mips == 64 )
  104. #define SH( u_val, p_dst ) \
  105. { \
  106. uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
  107. uint16_t u_val_h_m = ( u_val ); \
  108. \
  109. asm volatile ( \
  110. "sh %[u_val_h_m], %[p_dst_m] \n\t" \
  111. \
  112. : [p_dst_m] "=m" ( *p_dst_m ) \
  113. : [u_val_h_m] "r" ( u_val_h_m ) \
  114. ); \
  115. }
  116. #define SW( u_val, p_dst ) \
  117. { \
  118. uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
  119. uint32_t u_val_w_m = ( u_val ); \
  120. \
  121. asm volatile ( \
  122. "sw %[u_val_w_m], %[p_dst_m] \n\t" \
  123. \
  124. : [p_dst_m] "=m" ( *p_dst_m ) \
  125. : [u_val_w_m] "r" ( u_val_w_m ) \
  126. ); \
  127. }
  128. #define SD( u_val, p_dst ) \
  129. { \
  130. uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
  131. uint64_t u_val_d_m = ( u_val ); \
  132. \
  133. asm volatile ( \
  134. "sd %[u_val_d_m], %[p_dst_m] \n\t" \
  135. \
  136. : [p_dst_m] "=m" ( *p_dst_m ) \
  137. : [u_val_d_m] "r" ( u_val_d_m ) \
  138. ); \
  139. }
  140. #else // !( __mips_isa_rev >= 6 )
  141. #define LH( p_src ) \
  142. ( { \
  143. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  144. uint16_t u_val_h_m; \
  145. \
  146. asm volatile ( \
  147. "ulh %[u_val_h_m], %[p_src_m] \n\t" \
  148. \
  149. : [u_val_h_m] "=r" ( u_val_h_m ) \
  150. : [p_src_m] "m" ( *p_src_m ) \
  151. ); \
  152. \
  153. u_val_h_m; \
  154. } )
  155. #define LW( p_src ) \
  156. ( { \
  157. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  158. uint32_t u_val_w_m; \
  159. \
  160. asm volatile ( \
  161. "ulw %[u_val_w_m], %[p_src_m] \n\t" \
  162. \
  163. : [u_val_w_m] "=r" ( u_val_w_m ) \
  164. : [p_src_m] "m" ( *p_src_m ) \
  165. ); \
  166. \
  167. u_val_w_m; \
  168. } )
  169. #if ( __mips == 64 )
  170. #define LD( p_src ) \
  171. ( { \
  172. uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
  173. uint64_t u_val_d_m = 0; \
  174. \
  175. asm volatile ( \
  176. "uld %[u_val_d_m], %[p_src_m] \n\t" \
  177. \
  178. : [u_val_d_m] "=r" ( u_val_d_m ) \
  179. : [p_src_m] "m" ( *p_src_m ) \
  180. ); \
  181. \
  182. u_val_d_m; \
  183. } )
  184. #else // !( __mips == 64 )
  185. #define LD( p_src ) \
  186. ( { \
  187. uint8_t *psrc_m1 = ( uint8_t * ) ( p_src ); \
  188. uint32_t u_val0_m, u_val1_m; \
  189. uint64_t u_val_d_m = 0; \
  190. \
  191. u_val0_m = LW( psrc_m1 ); \
  192. u_val1_m = LW( psrc_m1 + 4 ); \
  193. \
  194. u_val_d_m = ( uint64_t ) ( u_val1_m ); \
  195. u_val_d_m = ( uint64_t ) ( ( u_val_d_m << 32 ) & \
  196. 0xFFFFFFFF00000000 ); \
  197. u_val_d_m = ( uint64_t ) ( u_val_d_m | ( uint64_t ) u_val0_m ); \
  198. \
  199. u_val_d_m; \
  200. } )
  201. #endif // ( __mips == 64 )
  202. #define SH( u_val, p_dst ) \
  203. { \
  204. uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
  205. uint16_t u_val_h_m = ( u_val ); \
  206. \
  207. asm volatile ( \
  208. "ush %[u_val_h_m], %[p_dst_m] \n\t" \
  209. \
  210. : [p_dst_m] "=m" ( *p_dst_m ) \
  211. : [u_val_h_m] "r" ( u_val_h_m ) \
  212. ); \
  213. }
  214. #define SW( u_val, p_dst ) \
  215. { \
  216. uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
  217. uint32_t u_val_w_m = ( u_val ); \
  218. \
  219. asm volatile ( \
  220. "usw %[u_val_w_m], %[p_dst_m] \n\t" \
  221. \
  222. : [p_dst_m] "=m" ( *p_dst_m ) \
  223. : [u_val_w_m] "r" ( u_val_w_m ) \
  224. ); \
  225. }
  226. #define SD( u_val, p_dst ) \
  227. { \
  228. uint8_t *p_dst_m1 = ( uint8_t * ) ( p_dst ); \
  229. uint32_t u_val0_m, u_val1_m; \
  230. \
  231. u_val0_m = ( uint32_t ) ( ( u_val ) & 0x00000000FFFFFFFF ); \
  232. u_val1_m = ( uint32_t ) ( ( ( u_val ) >> 32 ) & 0x00000000FFFFFFFF ); \
  233. \
  234. SW( u_val0_m, p_dst_m1 ); \
  235. SW( u_val1_m, p_dst_m1 + 4 ); \
  236. }
  237. #endif // ( __mips_isa_rev >= 6 )
  238. /* Description : Load 4 words with stride
  239. Arguments : Inputs - psrc (source pointer to load from)
  240. - stride
  241. Outputs - out0, out1, out2, out3
  242. Details : Load word in 'out0' from (psrc)
  243. Load word in 'out1' from (psrc + stride)
  244. Load word in 'out2' from (psrc + 2 * stride)
  245. Load word in 'out3' from (psrc + 3 * stride)
  246. */
  247. #define LW4( p_src, stride, out0, out1, out2, out3 ) \
  248. { \
  249. out0 = LW( ( p_src ) ); \
  250. out1 = LW( ( p_src ) + stride ); \
  251. out2 = LW( ( p_src ) + 2 * stride ); \
  252. out3 = LW( ( p_src ) + 3 * stride ); \
  253. }
  254. /* Description : Store 4 words with stride
  255. Arguments : Inputs - in0, in1, in2, in3, pdst, stride
  256. Details : Store word from 'in0' to (pdst)
  257. Store word from 'in1' to (pdst + stride)
  258. Store word from 'in2' to (pdst + 2 * stride)
  259. Store word from 'in3' to (pdst + 3 * stride)
  260. */
  261. #define SW4( in0, in1, in2, in3, p_dst, stride ) \
  262. { \
  263. SW( in0, ( p_dst ) ) \
  264. SW( in1, ( p_dst ) + stride ); \
  265. SW( in2, ( p_dst ) + 2 * stride ); \
  266. SW( in3, ( p_dst ) + 3 * stride ); \
  267. }
  268. /* Description : Store 4 double words with stride
  269. Arguments : Inputs - in0, in1, in2, in3, pdst, stride
  270. Details : Store double word from 'in0' to (pdst)
  271. Store double word from 'in1' to (pdst + stride)
  272. Store double word from 'in2' to (pdst + 2 * stride)
  273. Store double word from 'in3' to (pdst + 3 * stride)
  274. */
  275. #define SD4( in0, in1, in2, in3, p_dst, stride ) \
  276. { \
  277. SD( in0, ( p_dst ) ) \
  278. SD( in1, ( p_dst ) + stride ); \
  279. SD( in2, ( p_dst ) + 2 * stride ); \
  280. SD( in3, ( p_dst ) + 3 * stride ); \
  281. }
  282. /* Description : Load vectors with 16 byte elements with stride
  283. Arguments : Inputs - psrc (source pointer to load from)
  284. - stride
  285. Outputs - out0, out1
  286. Return Type - as per RTYPE
  287. Details : Load 16 byte elements in 'out0' from (psrc)
  288. Load 16 byte elements in 'out1' from (psrc + stride)
  289. */
  290. #define LD_B2( RTYPE, p_src, stride, out0, out1 ) \
  291. { \
  292. out0 = LD_B( RTYPE, ( p_src ) ); \
  293. out1 = LD_B( RTYPE, ( p_src ) + stride ); \
  294. }
  295. #define LD_UB2( ... ) LD_B2( v16u8, __VA_ARGS__ )
  296. #define LD_SB2( ... ) LD_B2( v16i8, __VA_ARGS__ )
  297. #define LD_B3( RTYPE, p_src, stride, out0, out1, out2 ) \
  298. { \
  299. LD_B2( RTYPE, ( p_src ), stride, out0, out1 ); \
  300. out2 = LD_B( RTYPE, ( p_src ) + 2 * stride ); \
  301. }
  302. #define LD_UB3( ... ) LD_B3( v16u8, __VA_ARGS__ )
  303. #define LD_SB3( ... ) LD_B3( v16i8, __VA_ARGS__ )
  304. #define LD_B4( RTYPE, p_src, stride, out0, out1, out2, out3 ) \
  305. { \
  306. LD_B2( RTYPE, ( p_src ), stride, out0, out1 ); \
  307. LD_B2( RTYPE, ( p_src ) + 2 * stride , stride, out2, out3 ); \
  308. }
  309. #define LD_UB4( ... ) LD_B4( v16u8, __VA_ARGS__ )
  310. #define LD_SB4( ... ) LD_B4( v16i8, __VA_ARGS__ )
  311. #define LD_B5( RTYPE, p_src, stride, out0, out1, out2, out3, out4 ) \
  312. { \
  313. LD_B4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
  314. out4 = LD_B( RTYPE, ( p_src ) + 4 * stride ); \
  315. }
  316. #define LD_UB5( ... ) LD_B5( v16u8, __VA_ARGS__ )
  317. #define LD_SB5( ... ) LD_B5( v16i8, __VA_ARGS__ )
  318. #define LD_B8( RTYPE, p_src, stride, \
  319. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  320. { \
  321. LD_B4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
  322. LD_B4( RTYPE, ( p_src ) + 4 * stride, stride, out4, out5, out6, out7 ); \
  323. }
  324. #define LD_UB8( ... ) LD_B8( v16u8, __VA_ARGS__ )
  325. #define LD_SB8( ... ) LD_B8( v16i8, __VA_ARGS__ )
  326. /* Description : Load vectors with 8 halfword elements with stride
  327. Arguments : Inputs - psrc (source pointer to load from)
  328. - stride
  329. Outputs - out0, out1
  330. Details : Load 8 halfword elements in 'out0' from (psrc)
  331. Load 8 halfword elements in 'out1' from (psrc + stride)
  332. */
  333. #define LD_H2( RTYPE, p_src, stride, out0, out1 ) \
  334. { \
  335. out0 = LD_H( RTYPE, ( p_src ) ); \
  336. out1 = LD_H( RTYPE, ( p_src ) + ( stride ) ); \
  337. }
  338. #define LD_SH2( ... ) LD_H2( v8i16, __VA_ARGS__ )
  339. #define LD_H4( RTYPE, p_src, stride, out0, out1, out2, out3 ) \
  340. { \
  341. LD_H2( RTYPE, ( p_src ), stride, out0, out1 ); \
  342. LD_H2( RTYPE, ( p_src ) + 2 * stride, stride, out2, out3 ); \
  343. }
  344. #define LD_SH4( ... ) LD_H4( v8i16, __VA_ARGS__ )
  345. #define LD_H8( RTYPE, p_src, stride, \
  346. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  347. { \
  348. LD_H4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
  349. LD_H4( RTYPE, ( p_src ) + 4 * stride, stride, out4, out5, out6, out7 ); \
  350. }
  351. #define LD_SH8( ... ) LD_H8( v8i16, __VA_ARGS__ )
  352. /* Description : Load 4x4 block of signed halfword elements from 1D source
  353. data into 4 vectors (Each vector with 4 signed halfwords)
  354. Arguments : Inputs - psrc
  355. Outputs - out0, out1, out2, out3
  356. */
  357. #define LD4x4_SH( p_src, out0, out1, out2, out3 ) \
  358. { \
  359. out0 = LD_SH( p_src ); \
  360. out2 = LD_SH( p_src + 8 ); \
  361. out1 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out0 ); \
  362. out3 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out2, ( v2i64 ) out2 ); \
  363. }
  364. /* Description : Load 2 vectors of signed word elements with stride
  365. Arguments : Inputs - psrc (source pointer to load from)
  366. - stride
  367. Outputs - out0, out1
  368. Return Type - signed word
  369. */
  370. #define LD_SW2( p_src, stride, out0, out1 ) \
  371. { \
  372. out0 = LD_SW( ( p_src ) ); \
  373. out1 = LD_SW( ( p_src ) + stride ); \
  374. }
  375. /* Description : Store vectors of 16 byte elements with stride
  376. Arguments : Inputs - in0, in1, stride
  377. - pdst (destination pointer to store to)
  378. Details : Store 16 byte elements from 'in0' to (pdst)
  379. Store 16 byte elements from 'in1' to (pdst + stride)
  380. */
  381. #define ST_B2( RTYPE, in0, in1, p_dst, stride ) \
  382. { \
  383. ST_B( RTYPE, in0, ( p_dst ) ); \
  384. ST_B( RTYPE, in1, ( p_dst ) + stride ); \
  385. }
  386. #define ST_UB2( ... ) ST_B2( v16u8, __VA_ARGS__ )
  387. #define ST_B4( RTYPE, in0, in1, in2, in3, p_dst, stride ) \
  388. { \
  389. ST_B2( RTYPE, in0, in1, ( p_dst ), stride ); \
  390. ST_B2( RTYPE, in2, in3, ( p_dst ) + 2 * stride, stride ); \
  391. }
  392. #define ST_UB4( ... ) ST_B4( v16u8, __VA_ARGS__ )
  393. #define ST_SB4( ... ) ST_B4( v16i8, __VA_ARGS__ )
  394. #define ST_B8( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  395. p_dst, stride ) \
  396. { \
  397. ST_B4( RTYPE, in0, in1, in2, in3, p_dst, stride ); \
  398. ST_B4( RTYPE, in4, in5, in6, in7, ( p_dst ) + 4 * stride, stride ); \
  399. }
  400. #define ST_UB8( ... ) ST_B8( v16u8, __VA_ARGS__ )
  401. /* Description : Store vectors of 8 halfword elements with stride
  402. Arguments : Inputs - in0, in1, stride
  403. - pdst (destination pointer to store to)
  404. Details : Store 8 halfword elements from 'in0' to (pdst)
  405. Store 8 halfword elements from 'in1' to (pdst + stride)
  406. */
  407. #define ST_H2( RTYPE, in0, in1, p_dst, stride ) \
  408. { \
  409. ST_H( RTYPE, in0, ( p_dst ) ); \
  410. ST_H( RTYPE, in1, ( p_dst ) + stride ); \
  411. }
  412. #define ST_SH2( ... ) ST_H2( v8i16, __VA_ARGS__ )
  413. #define ST_H4( RTYPE, in0, in1, in2, in3, p_dst, stride ) \
  414. { \
  415. ST_H2( RTYPE, in0, in1, ( p_dst ), stride ); \
  416. ST_H2( RTYPE, in2, in3, ( p_dst ) + 2 * stride, stride ); \
  417. }
  418. #define ST_SH4( ... ) ST_H4( v8i16, __VA_ARGS__ )
  419. #define ST_H8( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, p_dst, stride ) \
  420. { \
  421. ST_H4( RTYPE, in0, in1, in2, in3, ( p_dst ), stride ); \
  422. ST_H4( RTYPE, in4, in5, in6, in7, ( p_dst ) + 4 * stride, stride ); \
  423. }
  424. #define ST_SH8( ... ) ST_H8( v8i16, __VA_ARGS__ )
  425. /* Description : Store 2x4 byte block to destination memory from input vector
  426. Arguments : Inputs - in, stidx, pdst, stride
  427. Details : Index 'stidx' halfword element from 'in' vector is copied to
  428. GP register and stored to (pdst)
  429. Index 'stidx+1' halfword element from 'in' vector is copied to
  430. GP register and stored to (pdst + stride)
  431. Index 'stidx+2' halfword element from 'in' vector is copied to
  432. GP register and stored to (pdst + 2 * stride)
  433. Index 'stidx+3' halfword element from 'in' vector is copied to
  434. GP register and stored to (pdst + 3 * stride)
  435. */
  436. #define ST2x4_UB( in, stidx, p_dst, stride ) \
  437. { \
  438. uint16_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
  439. uint8_t *pblk_2x4_m = ( uint8_t * ) ( p_dst ); \
  440. \
  441. u_out0_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx ) ); \
  442. u_out1_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 1 ) ); \
  443. u_out2_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 2 ) ); \
  444. u_out3_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 3 ) ); \
  445. \
  446. SH( u_out0_m, pblk_2x4_m ); \
  447. SH( u_out1_m, pblk_2x4_m + stride ); \
  448. SH( u_out2_m, pblk_2x4_m + 2 * stride ); \
  449. SH( u_out3_m, pblk_2x4_m + 3 * stride ); \
  450. }
  451. /* Description : Store 4x4 byte block to destination memory from input vector
  452. Arguments : Inputs - in0, in1, pdst, stride
  453. Details : 'Idx0' word element from input vector 'in0' is copied to
  454. GP register and stored to (pdst)
  455. 'Idx1' word element from input vector 'in0' is copied to
  456. GP register and stored to (pdst + stride)
  457. 'Idx2' word element from input vector 'in0' is copied to
  458. GP register and stored to (pdst + 2 * stride)
  459. 'Idx3' word element from input vector 'in0' is copied to
  460. GP register and stored to (pdst + 3 * stride)
  461. */
  462. #define ST4x4_UB( in0, in1, idx0, idx1, idx2, idx3, p_dst, stride ) \
  463. { \
  464. uint32_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
  465. uint8_t *pblk_4x4_m = ( uint8_t * ) ( p_dst ); \
  466. \
  467. u_out0_m = __msa_copy_u_w( ( v4i32 ) in0, idx0 ); \
  468. u_out1_m = __msa_copy_u_w( ( v4i32 ) in0, idx1 ); \
  469. u_out2_m = __msa_copy_u_w( ( v4i32 ) in1, idx2 ); \
  470. u_out3_m = __msa_copy_u_w( ( v4i32 ) in1, idx3 ); \
  471. \
  472. SW4( u_out0_m, u_out1_m, u_out2_m, u_out3_m, pblk_4x4_m, stride ); \
  473. }
  474. #define ST4x8_UB( in0, in1, p_dst, stride ) \
  475. { \
  476. uint8_t *pblk_4x8 = ( uint8_t * ) ( p_dst ); \
  477. \
  478. ST4x4_UB( in0, in0, 0, 1, 2, 3, pblk_4x8, stride ); \
  479. ST4x4_UB( in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride ); \
  480. }
  481. /* Description : Store 8x1 byte block to destination memory from input vector
  482. Arguments : Inputs - in, pdst
  483. Details : Index 0 double word element from 'in' vector is copied to
  484. GP register and stored to (pdst)
  485. */
  486. #define ST8x1_UB( in, p_dst ) \
  487. { \
  488. uint64_t u_out0_m; \
  489. u_out0_m = __msa_copy_u_d( ( v2i64 ) in, 0 ); \
  490. SD( u_out0_m, p_dst ); \
  491. }
  492. /* Description : Store 8x4 byte block to destination memory from input
  493. vectors
  494. Arguments : Inputs - in0, in1, pdst, stride
  495. Details : Index 0 double word element from 'in0' vector is copied to
  496. GP register and stored to (pdst)
  497. Index 1 double word element from 'in0' vector is copied to
  498. GP register and stored to (pdst + stride)
  499. Index 0 double word element from 'in1' vector is copied to
  500. GP register and stored to (pdst + 2 * stride)
  501. Index 1 double word element from 'in1' vector is copied to
  502. GP register and stored to (pdst + 3 * stride)
  503. */
  504. #define ST8x4_UB( in0, in1, p_dst, stride ) \
  505. { \
  506. uint64_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
  507. uint8_t *pblk_8x4_m = ( uint8_t * ) ( p_dst ); \
  508. \
  509. u_out0_m = __msa_copy_u_d( ( v2i64 ) in0, 0 ); \
  510. u_out1_m = __msa_copy_u_d( ( v2i64 ) in0, 1 ); \
  511. u_out2_m = __msa_copy_u_d( ( v2i64 ) in1, 0 ); \
  512. u_out3_m = __msa_copy_u_d( ( v2i64 ) in1, 1 ); \
  513. \
  514. SD4( u_out0_m, u_out1_m, u_out2_m, u_out3_m, pblk_8x4_m, stride ); \
  515. }
  516. /* Description : average with rounding (in0 + in1 + 1) / 2.
  517. Arguments : Inputs - in0, in1, in2, in3,
  518. Outputs - out0, out1
  519. Return Type - as per RTYPE
  520. Details : Each unsigned byte element from 'in0' vector is added with
  521. each unsigned byte element from 'in1' vector.
  522. Average with rounding is calculated and written to 'out0'
  523. */
  524. #define AVER_UB2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  525. { \
  526. out0 = ( RTYPE ) __msa_aver_u_b( ( v16u8 ) in0, ( v16u8 ) in1 ); \
  527. out1 = ( RTYPE ) __msa_aver_u_b( ( v16u8 ) in2, ( v16u8 ) in3 ); \
  528. }
  529. #define AVER_UB2_UB( ... ) AVER_UB2( v16u8, __VA_ARGS__ )
  530. #define AVER_UB4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  531. out0, out1, out2, out3 ) \
  532. { \
  533. AVER_UB2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  534. AVER_UB2( RTYPE, in4, in5, in6, in7, out2, out3 ) \
  535. }
  536. #define AVER_UB4_UB( ... ) AVER_UB4( v16u8, __VA_ARGS__ )
  537. /* Description : Immediate number of elements to slide with zero
  538. Arguments : Inputs - in0, in1, slide_val
  539. Outputs - out0, out1
  540. Return Type - as per RTYPE
  541. Details : Byte elements from 'zero_m' vector are slide into 'in0' by
  542. value specified in 'slide_val'
  543. */
  544. #define SLDI_B2_0( RTYPE, in0, in1, out0, out1, slide_val ) \
  545. { \
  546. v16i8 zero_m = { 0 }; \
  547. out0 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) zero_m, \
  548. ( v16i8 ) in0, slide_val ); \
  549. out1 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) zero_m, \
  550. ( v16i8 ) in1, slide_val ); \
  551. }
  552. #define SLDI_B2_0_UB( ... ) SLDI_B2_0( v16u8, __VA_ARGS__ )
  553. /* Description : Immediate number of elements to slide
  554. Arguments : Inputs - in0_0, in0_1, in1_0, in1_1, slide_val
  555. Outputs - out0, out1
  556. Return Type - as per RTYPE
  557. Details : Byte elements from 'in0_0' vector are slide into 'in1_0' by
  558. value specified in 'slide_val'
  559. */
  560. #define SLDI_B2( RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val ) \
  561. { \
  562. out0 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) in0_0, ( v16i8 ) in1_0, \
  563. slide_val ); \
  564. out1 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) in0_1, ( v16i8 ) in1_1, \
  565. slide_val ); \
  566. }
  567. #define SLDI_B2_UB( ... ) SLDI_B2( v16u8, __VA_ARGS__ )
  568. /* Description : Shuffle byte vector elements as per mask vector
  569. Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
  570. Outputs - out0, out1
  571. Return Type - as per RTYPE
  572. Details : Selective byte elements from 'in0' & 'in1' are copied to
  573. 'out0' as per control vector 'mask0'
  574. */
  575. #define VSHF_B2( RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1 ) \
  576. { \
  577. out0 = ( RTYPE ) __msa_vshf_b( ( v16i8 ) mask0, \
  578. ( v16i8 ) in1, ( v16i8 ) in0 ); \
  579. out1 = ( RTYPE ) __msa_vshf_b( ( v16i8 ) mask1, \
  580. ( v16i8 ) in3, ( v16i8 ) in2 ); \
  581. }
  582. #define VSHF_B2_UB( ... ) VSHF_B2( v16u8, __VA_ARGS__ )
  583. #define VSHF_B2_SB( ... ) VSHF_B2( v16i8, __VA_ARGS__ )
  584. /* Description : Shuffle halfword vector elements as per mask vector
  585. Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
  586. Outputs - out0, out1
  587. Return Type - as per RTYPE
  588. Details : Selective byte elements from 'in0' & 'in1' are copied to
  589. 'out0' as per control vector 'mask0'
  590. */
  591. #define VSHF_H2( RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1 ) \
  592. { \
  593. out0 = ( RTYPE ) __msa_vshf_h( ( v8i16 ) mask0, \
  594. ( v8i16 ) in1, ( v8i16 ) in0 ); \
  595. out1 = ( RTYPE ) __msa_vshf_h( ( v8i16 ) mask1, \
  596. ( v8i16 ) in3, ( v8i16 ) in2 ); \
  597. }
  598. #define VSHF_H2_SH( ... ) VSHF_H2( v8i16, __VA_ARGS__ )
  599. /* Description : Dot product of byte vector elements
  600. Arguments : Inputs - mult0, mult1
  601. cnst0, cnst1
  602. Outputs - out0, out1
  603. Return Type - as per RTYPE
  604. Details : Unsigned byte elements from 'mult0' are multiplied with
  605. unsigned byte elements from 'cnst0' producing a result
  606. twice the size of input i.e. unsigned halfword.
  607. Multiplication result of adjacent odd-even elements
  608. are added together and written to the 'out0' vector
  609. */
  610. #define DOTP_UB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
  611. { \
  612. out0 = ( RTYPE ) __msa_dotp_u_h( ( v16u8 ) mult0, ( v16u8 ) cnst0 ); \
  613. out1 = ( RTYPE ) __msa_dotp_u_h( ( v16u8 ) mult1, ( v16u8 ) cnst1 ); \
  614. }
  615. #define DOTP_UB2_UH( ... ) DOTP_UB2( v8u16, __VA_ARGS__ )
  616. #define DOTP_UB4( RTYPE, mult0, mult1, mult2, mult3, \
  617. cnst0, cnst1, cnst2, cnst3, \
  618. out0, out1, out2, out3 ) \
  619. { \
  620. DOTP_UB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ); \
  621. DOTP_UB2( RTYPE, mult2, mult3, cnst2, cnst3, out2, out3 ); \
  622. }
  623. #define DOTP_UB4_UH( ... ) DOTP_UB4( v8u16, __VA_ARGS__ )
  624. /* Description : Dot product of byte vector elements
  625. Arguments : Inputs - mult0, mult1
  626. cnst0, cnst1
  627. Outputs - out0, out1
  628. Return Type - as per RTYPE
  629. Details : Signed byte elements from 'mult0' are multiplied with
  630. signed byte elements from 'cnst0' producing a result
  631. twice the size of input i.e. signed halfword.
  632. Multiplication result of adjacent odd-even elements
  633. are added together and written to the 'out0' vector
  634. */
  635. #define DPADD_SB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
  636. { \
  637. out0 = ( RTYPE ) __msa_dpadd_s_h( ( v8i16 ) out0, \
  638. ( v16i8 ) mult0, ( v16i8 ) cnst0 ); \
  639. out1 = ( RTYPE ) __msa_dpadd_s_h( ( v8i16 ) out1, \
  640. ( v16i8 ) mult1, ( v16i8 ) cnst1 ); \
  641. }
  642. #define DPADD_SB2_SH( ... ) DPADD_SB2( v8i16, __VA_ARGS__ )
  643. #define DPADD_SB4( RTYPE, mult0, mult1, mult2, mult3, \
  644. cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3 ) \
  645. { \
  646. DPADD_SB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ); \
  647. DPADD_SB2( RTYPE, mult2, mult3, cnst2, cnst3, out2, out3 ); \
  648. }
  649. #define DPADD_SB4_SH( ... ) DPADD_SB4( v8i16, __VA_ARGS__ )
  650. /* Description : Dot product of halfword vector elements
  651. Arguments : Inputs - mult0, mult1
  652. cnst0, cnst1
  653. Outputs - out0, out1
  654. Return Type - as per RTYPE
  655. Details : Signed halfword elements from 'mult0' are multiplied with
  656. signed halfword elements from 'cnst0' producing a result
  657. twice the size of input i.e. signed word.
  658. Multiplication result of adjacent odd-even elements
  659. are added together and written to the 'out0' vector
  660. */
  661. #define DPADD_SH2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
  662. { \
  663. out0 = ( RTYPE ) __msa_dpadd_s_w( ( v4i32 ) out0, \
  664. ( v8i16 ) mult0, ( v8i16 ) cnst0 ); \
  665. out1 = ( RTYPE ) __msa_dpadd_s_w( ( v4i32 ) out1, \
  666. ( v8i16 ) mult1, ( v8i16 ) cnst1 ); \
  667. }
  668. #define DPADD_SH2_SW( ... ) DPADD_SH2( v4i32, __VA_ARGS__ )
  669. /* Description : Clips all halfword elements of input vector between min & max
  670. out = (in < min) ? min : ((in > max) ? max : in)
  671. Arguments : Inputs - in, min, max
  672. Output - out_m
  673. Return Type - signed halfword
  674. */
  675. #define CLIP_SH( in, min, max ) \
  676. ( { \
  677. v8i16 out_m; \
  678. \
  679. out_m = __msa_max_s_h( ( v8i16 ) min, ( v8i16 ) in ); \
  680. out_m = __msa_min_s_h( ( v8i16 ) max, ( v8i16 ) out_m ); \
  681. out_m; \
  682. } )
  683. /* Description : Clips all signed halfword elements of input vector
  684. between 0 & 255
  685. Arguments : Input - in
  686. Output - out_m
  687. Return Type - signed halfword
  688. */
  689. #define CLIP_SH_0_255( in ) \
  690. ( { \
  691. v8i16 max_m = __msa_ldi_h( 255 ); \
  692. v8i16 out_m; \
  693. \
  694. out_m = __msa_maxi_s_h( ( v8i16 ) in, 0 ); \
  695. out_m = __msa_min_s_h( ( v8i16 ) max_m, ( v8i16 ) out_m ); \
  696. out_m; \
  697. } )
  698. #define CLIP_SH2_0_255( in0, in1 ) \
  699. { \
  700. in0 = CLIP_SH_0_255( in0 ); \
  701. in1 = CLIP_SH_0_255( in1 ); \
  702. }
  703. #define CLIP_SH4_0_255( in0, in1, in2, in3 ) \
  704. { \
  705. CLIP_SH2_0_255( in0, in1 ); \
  706. CLIP_SH2_0_255( in2, in3 ); \
  707. }
  708. /* Description : Horizontal addition of 4 signed word elements of input vector
  709. Arguments : Input - in (signed word vector)
  710. Output - sum_m (i32 sum)
  711. Return Type - signed word (GP)
  712. Details : 4 signed word elements of 'in' vector are added together and
  713. the resulting integer sum is returned
  714. */
  715. #define HADD_SW_S32( in ) \
  716. ( { \
  717. v2i64 res0_m, res1_m; \
  718. int32_t i_sum_m; \
  719. \
  720. res0_m = __msa_hadd_s_d( ( v4i32 ) in, ( v4i32 ) in ); \
  721. res1_m = __msa_splati_d( res0_m, 1 ); \
  722. res0_m = res0_m + res1_m; \
  723. i_sum_m = __msa_copy_s_w( ( v4i32 ) res0_m, 0 ); \
  724. i_sum_m; \
  725. } )
  726. /* Description : Horizontal addition of 4 signed word elements of input vector
  727. Arguments : Input - in (signed word vector)
  728. Output - sum_m (i32 sum)
  729. Return Type - signed word (GP)
  730. Details : 4 signed word elements of 'in' vector are added together and
  731. the resulting integer sum is returned
  732. */
  733. #define HADD_UH_U32( in ) \
  734. ( { \
  735. v4u32 res_m; \
  736. v2u64 res0_m, res1_m; \
  737. uint32_t u_sum_m; \
  738. \
  739. res_m = __msa_hadd_u_w( ( v8u16 ) in, ( v8u16 ) in ); \
  740. res0_m = __msa_hadd_u_d( res_m, res_m ); \
  741. res1_m = ( v2u64 ) __msa_splati_d( ( v2i64 ) res0_m, 1 ); \
  742. res0_m = res0_m + res1_m; \
  743. u_sum_m = __msa_copy_u_w( ( v4i32 ) res0_m, 0 ); \
  744. u_sum_m; \
  745. } )
  746. /* Description : Horizontal addition of signed byte vector elements
  747. Arguments : Inputs - in0, in1
  748. Outputs - out0, out1
  749. Return Type - as per RTYPE
  750. Details : Each signed odd byte element from 'in0' is added to
  751. even signed byte element from 'in0' (pairwise) and the
  752. halfword result is written in 'out0'
  753. */
  754. #define HADD_SB2( RTYPE, in0, in1, out0, out1 ) \
  755. { \
  756. out0 = ( RTYPE ) __msa_hadd_s_h( ( v16i8 ) in0, ( v16i8 ) in0 ); \
  757. out1 = ( RTYPE ) __msa_hadd_s_h( ( v16i8 ) in1, ( v16i8 ) in1 ); \
  758. }
  759. #define HADD_SB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
  760. { \
  761. HADD_SB2( RTYPE, in0, in1, out0, out1 ); \
  762. HADD_SB2( RTYPE, in2, in3, out2, out3 ); \
  763. }
  764. #define HADD_SB4_SH( ... ) HADD_SB4( v8i16, __VA_ARGS__ )
  765. /* Description : Horizontal addition of unsigned byte vector elements
  766. Arguments : Inputs - in0, in1
  767. Outputs - out0, out1
  768. Return Type - as per RTYPE
  769. Details : Each unsigned odd byte element from 'in0' is added to
  770. even unsigned byte element from 'in0' (pairwise) and the
  771. halfword result is written to 'out0'
  772. */
  773. #define HADD_UB2( RTYPE, in0, in1, out0, out1 ) \
  774. { \
  775. out0 = ( RTYPE ) __msa_hadd_u_h( ( v16u8 ) in0, ( v16u8 ) in0 ); \
  776. out1 = ( RTYPE ) __msa_hadd_u_h( ( v16u8 ) in1, ( v16u8 ) in1 ); \
  777. }
  778. #define HADD_UB2_UH( ... ) HADD_UB2( v8u16, __VA_ARGS__ )
  779. #define HADD_UB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
  780. { \
  781. HADD_UB2( RTYPE, in0, in1, out0, out1 ); \
  782. HADD_UB2( RTYPE, in2, in3, out2, out3 ); \
  783. }
  784. #define HADD_UB4_UH( ... ) HADD_UB4( v8u16, __VA_ARGS__ )
  785. /* Description : Horizontal subtraction of unsigned byte vector elements
  786. Arguments : Inputs - in0, in1
  787. Outputs - out0, out1
  788. Return Type - as per RTYPE
  789. Details : Each unsigned odd byte element from 'in0' is subtracted from
  790. even unsigned byte element from 'in0' (pairwise) and the
  791. halfword result is written to 'out0'
  792. */
  793. #define HSUB_UB2( RTYPE, in0, in1, out0, out1 ) \
  794. { \
  795. out0 = ( RTYPE ) __msa_hsub_u_h( ( v16u8 ) in0, ( v16u8 ) in0 ); \
  796. out1 = ( RTYPE ) __msa_hsub_u_h( ( v16u8 ) in1, ( v16u8 ) in1 ); \
  797. }
  798. #define HSUB_UB2_SH( ... ) HSUB_UB2( v8i16, __VA_ARGS__ )
  799. #define HSUB_UB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
  800. { \
  801. HSUB_UB2( RTYPE, in0, in1, out0, out1 ); \
  802. HSUB_UB2( RTYPE, in2, in3, out2, out3 ); \
  803. }
  804. #define HSUB_UB4_SH( ... ) HSUB_UB4( v8i16, __VA_ARGS__ )
  805. /* Description : SAD (Sum of Absolute Difference)
  806. Arguments : Inputs - in0, in1, ref0, ref1
  807. Outputs - sad_m (halfword vector)
  808. Return Type - unsigned halfword
  809. Details : Absolute difference of all the byte elements from 'in0' with
  810. 'ref0' is calculated and preserved in 'diff0'. Then even-odd
  811. pairs are added together to generate 8 halfword results.
  812. */
  813. #define SAD_UB2_UH( in0, in1, ref0, ref1 ) \
  814. ( { \
  815. v16u8 diff0_m, diff1_m; \
  816. v8u16 sad_m = { 0 }; \
  817. \
  818. diff0_m = __msa_asub_u_b( ( v16u8 ) in0, ( v16u8 ) ref0 ); \
  819. diff1_m = __msa_asub_u_b( ( v16u8 ) in1, ( v16u8 ) ref1 ); \
  820. \
  821. sad_m += __msa_hadd_u_h( ( v16u8 ) diff0_m, ( v16u8 ) diff0_m ); \
  822. sad_m += __msa_hadd_u_h( ( v16u8 ) diff1_m, ( v16u8 ) diff1_m ); \
  823. \
  824. sad_m; \
  825. } )
  826. /* Description : Set element n input vector to GPR value
  827. Arguments : Inputs - in0, in1, in2, in3 (4 input vectors)
  828. Output - out (output vector)
  829. Return Type - as per RTYPE
  830. Details : Set element 0 in vector 'out' to value specified in 'in0'
  831. */
  832. #define INSERT_W2( RTYPE, in0, in1, out ) \
  833. { \
  834. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 0, in0 ); \
  835. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 1, in1 ); \
  836. }
  837. #define INSERT_W2_SB( ... ) INSERT_W2( v16i8, __VA_ARGS__ )
  838. #define INSERT_W4( RTYPE, in0, in1, in2, in3, out ) \
  839. { \
  840. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 0, in0 ); \
  841. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 1, in1 ); \
  842. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 2, in2 ); \
  843. out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 3, in3 ); \
  844. }
  845. #define INSERT_W4_UB( ... ) INSERT_W4( v16u8, __VA_ARGS__ )
  846. #define INSERT_W4_SB( ... ) INSERT_W4( v16i8, __VA_ARGS__ )
  847. #define INSERT_D2( RTYPE, in0, in1, out ) \
  848. { \
  849. out = ( RTYPE ) __msa_insert_d( ( v2i64 ) out, 0, in0 ); \
  850. out = ( RTYPE ) __msa_insert_d( ( v2i64 ) out, 1, in1 ); \
  851. }
  852. #define INSERT_D2_UB( ... ) INSERT_D2( v16u8, __VA_ARGS__ )
  853. /* Description : Interleave even halfword elements from vectors
  854. Arguments : Inputs - in0, in1, in2, in3
  855. Outputs - out0, out1
  856. Return Type - as per RTYPE
  857. Details : Even halfword elements of 'in0' and 'in1' are interleaved
  858. and written to 'out0'
  859. */
  860. #define ILVEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  861. { \
  862. out0 = ( RTYPE ) __msa_ilvev_h( ( v8i16 ) in1, ( v8i16 ) in0 ); \
  863. out1 = ( RTYPE ) __msa_ilvev_h( ( v8i16 ) in3, ( v8i16 ) in2 ); \
  864. }
  865. #define ILVEV_H2_UB( ... ) ILVEV_H2( v16u8, __VA_ARGS__ )
  866. /* Description : Interleave even double word elements from vectors
  867. Arguments : Inputs - in0, in1, in2, in3
  868. Outputs - out0, out1
  869. Return Type - as per RTYPE
  870. Details : Even double word elements of 'in0' and 'in1' are interleaved
  871. and written to 'out0'
  872. */
  873. #define ILVEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  874. { \
  875. out0 = ( RTYPE ) __msa_ilvev_d( ( v2i64 ) in1, ( v2i64 ) in0 ); \
  876. out1 = ( RTYPE ) __msa_ilvev_d( ( v2i64 ) in3, ( v2i64 ) in2 ); \
  877. }
  878. #define ILVEV_D2_UB( ... ) ILVEV_D2( v16u8, __VA_ARGS__ )
  879. /* Description : Interleave left half of byte elements from vectors
  880. Arguments : Inputs - in0, in1, in2, in3
  881. Outputs - out0, out1
  882. Return Type - as per RTYPE
  883. Details : Left half of byte elements of 'in0' and 'in1' are interleaved
  884. and written to 'out0'.
  885. */
  886. #define ILVL_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  887. { \
  888. out0 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  889. out1 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
  890. }
  891. #define ILVL_B2_UH( ... ) ILVL_B2( v8u16, __VA_ARGS__ )
  892. #define ILVL_B2_SH( ... ) ILVL_B2( v8i16, __VA_ARGS__ )
  893. #define ILVL_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  894. out0, out1, out2, out3 ) \
  895. { \
  896. ILVL_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  897. ILVL_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  898. }
  899. #define ILVL_B4_UB( ... ) ILVL_B4( v16u8, __VA_ARGS__ )
  900. #define ILVL_B4_SB( ... ) ILVL_B4( v16i8, __VA_ARGS__ )
  901. #define ILVL_B4_UH( ... ) ILVL_B4( v8u16, __VA_ARGS__ )
  902. #define ILVL_B4_SH( ... ) ILVL_B4( v8i16, __VA_ARGS__ )
  903. /* Description : Interleave left half of halfword elements from vectors
  904. Arguments : Inputs - in0, in1, in2, in3
  905. Outputs - out0, out1
  906. Return Type - as per RTYPE
  907. Details : Left half of halfword elements of 'in0' and 'in1' are
  908. interleaved and written to 'out0'.
  909. */
  910. #define ILVL_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  911. { \
  912. out0 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  913. out1 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
  914. }
  915. #define ILVL_H2_SH( ... ) ILVL_H2( v8i16, __VA_ARGS__ )
  916. #define ILVL_H2_SW( ... ) ILVL_H2( v4i32, __VA_ARGS__ )
  917. #define ILVL_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  918. out0, out1, out2, out3 ) \
  919. { \
  920. ILVL_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  921. ILVL_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  922. }
  923. #define ILVL_H4_SW( ... ) ILVL_H4( v4i32, __VA_ARGS__ )
  924. /* Description : Interleave left half of word elements from vectors
  925. Arguments : Inputs - in0, in1, in2, in3
  926. Outputs - out0, out1
  927. Return Type - as per RTYPE
  928. Details : Left half of word elements of 'in0' and 'in1' are interleaved
  929. and written to 'out0'.
  930. */
  931. #define ILVL_W2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  932. { \
  933. out0 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
  934. out1 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in2, ( v4i32 ) in3 ); \
  935. }
  936. #define ILVL_W2_SH( ... ) ILVL_W2( v8i16, __VA_ARGS__ )
  937. /* Description : Interleave right half of byte elements from vectors
  938. Arguments : Inputs - in0, in1, in2, in3
  939. Outputs - out0, out1
  940. Return Type - as per RTYPE
  941. Details : Right half of byte elements of 'in0' and 'in1' are interleaved
  942. and written to out0.
  943. */
  944. #define ILVR_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  945. { \
  946. out0 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  947. out1 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
  948. }
  949. #define ILVR_B2_SB( ... ) ILVR_B2( v16i8, __VA_ARGS__ )
  950. #define ILVR_B2_UH( ... ) ILVR_B2( v8u16, __VA_ARGS__ )
  951. #define ILVR_B2_SH( ... ) ILVR_B2( v8i16, __VA_ARGS__ )
  952. #define ILVR_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  953. out0, out1, out2, out3 ) \
  954. { \
  955. ILVR_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  956. ILVR_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  957. }
  958. #define ILVR_B4_UB( ... ) ILVR_B4( v16u8, __VA_ARGS__ )
  959. #define ILVR_B4_SB( ... ) ILVR_B4( v16i8, __VA_ARGS__ )
  960. #define ILVR_B4_UH( ... ) ILVR_B4( v8u16, __VA_ARGS__ )
  961. #define ILVR_B4_SH( ... ) ILVR_B4( v8i16, __VA_ARGS__ )
  962. /* Description : Interleave right half of halfword elements from vectors
  963. Arguments : Inputs - in0, in1, in2, in3
  964. Outputs - out0, out1
  965. Return Type - as per RTYPE
  966. Details : Right half of halfword elements of 'in0' and 'in1' are
  967. interleaved and written to 'out0'.
  968. */
  969. #define ILVR_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  970. { \
  971. out0 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  972. out1 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
  973. }
  974. #define ILVR_H2_SH( ... ) ILVR_H2( v8i16, __VA_ARGS__ )
  975. #define ILVR_H2_SW( ... ) ILVR_H2( v4i32, __VA_ARGS__ )
  976. #define ILVR_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  977. out0, out1, out2, out3 ) \
  978. { \
  979. ILVR_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  980. ILVR_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  981. }
  982. #define ILVR_H4_SH( ... ) ILVR_H4( v8i16, __VA_ARGS__ )
  983. #define ILVR_H4_SW( ... ) ILVR_H4( v4i32, __VA_ARGS__ )
  984. #define ILVR_W2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  985. { \
  986. out0 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
  987. out1 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in2, ( v4i32 ) in3 ); \
  988. }
  989. #define ILVR_W2_SH( ... ) ILVR_W2( v8i16, __VA_ARGS__ )
  990. /* Description : Interleave right half of double word elements from vectors
  991. Arguments : Inputs - in0, in1, in2, in3
  992. Outputs - out0, out1
  993. Return Type - as per RTYPE
  994. Details : Right half of double word elements of 'in0' and 'in1' are
  995. interleaved and written to 'out0'.
  996. */
  997. #define ILVR_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  998. { \
  999. out0 = ( RTYPE ) __msa_ilvr_d( ( v2i64 ) ( in0 ), ( v2i64 ) ( in1 ) ); \
  1000. out1 = ( RTYPE ) __msa_ilvr_d( ( v2i64 ) ( in2 ), ( v2i64 ) ( in3 ) ); \
  1001. }
  1002. #define ILVR_D2_UB( ... ) ILVR_D2( v16u8, __VA_ARGS__ )
  1003. #define ILVR_D2_SB( ... ) ILVR_D2( v16i8, __VA_ARGS__ )
  1004. #define ILVR_D2_SH( ... ) ILVR_D2( v8i16, __VA_ARGS__ )
  1005. #define ILVR_D4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1006. out0, out1, out2, out3 ) \
  1007. { \
  1008. ILVR_D2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1009. ILVR_D2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1010. }
  1011. #define ILVR_D4_UB( ... ) ILVR_D4( v16u8, __VA_ARGS__ )
  1012. /* Description : Interleave both left and right half of input vectors
  1013. Arguments : Inputs - in0, in1
  1014. Outputs - out0, out1
  1015. Return Type - as per RTYPE
  1016. Details : Right half of byte elements from 'in0' and 'in1' are
  1017. interleaved and written to 'out0'
  1018. */
  1019. #define ILVRL_B2( RTYPE, in0, in1, out0, out1 ) \
  1020. { \
  1021. out0 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  1022. out1 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  1023. }
  1024. #define ILVRL_B2_UB( ... ) ILVRL_B2( v16u8, __VA_ARGS__ )
  1025. #define ILVRL_B2_SB( ... ) ILVRL_B2( v16i8, __VA_ARGS__ )
  1026. #define ILVRL_B2_UH( ... ) ILVRL_B2( v8u16, __VA_ARGS__ )
  1027. #define ILVRL_B2_SH( ... ) ILVRL_B2( v8i16, __VA_ARGS__ )
  1028. #define ILVRL_B2_SW( ... ) ILVRL_B2( v4i32, __VA_ARGS__ )
  1029. #define ILVRL_H2( RTYPE, in0, in1, out0, out1 ) \
  1030. { \
  1031. out0 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  1032. out1 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  1033. }
  1034. #define ILVRL_H2_SH( ... ) ILVRL_H2( v8i16, __VA_ARGS__ )
  1035. #define ILVRL_H2_SW( ... ) ILVRL_H2( v4i32, __VA_ARGS__ )
  1036. #define ILVRL_W2( RTYPE, in0, in1, out0, out1 ) \
  1037. { \
  1038. out0 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
  1039. out1 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
  1040. }
  1041. #define ILVRL_W2_SH( ... ) ILVRL_W2( v8i16, __VA_ARGS__ )
  1042. #define ILVRL_W2_SW( ... ) ILVRL_W2( v4i32, __VA_ARGS__ )
  1043. /* Description : Maximum values between signed elements of vector and
  1044. 5-bit signed immediate value are copied to the output vector
  1045. Arguments : Inputs - in0, in1, in2, in3, max_val
  1046. Outputs - in place operation
  1047. Return Type - unsigned halfword
  1048. Details : Maximum of signed halfword element values from 'in0' and
  1049. 'max_val' are written in place
  1050. */
  1051. #define MAXI_SH2( RTYPE, in0, in1, max_val ) \
  1052. { \
  1053. in0 = ( RTYPE ) __msa_maxi_s_h( ( v8i16 ) in0, ( max_val ) ); \
  1054. in1 = ( RTYPE ) __msa_maxi_s_h( ( v8i16 ) in1, ( max_val ) ); \
  1055. }
  1056. #define MAXI_SH2_UH( ... ) MAXI_SH2( v8u16, __VA_ARGS__ )
  1057. #define MAXI_SH2_SH( ... ) MAXI_SH2( v8i16, __VA_ARGS__ )
  1058. #define MAXI_SH4( RTYPE, in0, in1, in2, in3, max_val ) \
  1059. { \
  1060. MAXI_SH2( RTYPE, in0, in1, max_val ); \
  1061. MAXI_SH2( RTYPE, in2, in3, max_val ); \
  1062. }
  1063. #define MAXI_SH4_UH( ... ) MAXI_SH4( v8u16, __VA_ARGS__ )
  1064. /* Description : Saturate the halfword element values to the max
  1065. unsigned value of (sat_val + 1 bits)
  1066. The element data width remains unchanged
  1067. Arguments : Inputs - in0, in1, sat_val
  1068. Outputs - in place operation
  1069. Return Type - as per RTYPE
  1070. Details : Each unsigned halfword element from 'in0' is saturated to the
  1071. value generated with (sat_val+1) bit range.
  1072. The results are written in place
  1073. */
  1074. #define SAT_UH2( RTYPE, in0, in1, sat_val ) \
  1075. { \
  1076. in0 = ( RTYPE ) __msa_sat_u_h( ( v8u16 ) in0, sat_val ); \
  1077. in1 = ( RTYPE ) __msa_sat_u_h( ( v8u16 ) in1, sat_val ); \
  1078. }
  1079. #define SAT_UH2_UH( ... ) SAT_UH2( v8u16, __VA_ARGS__ )
  1080. #define SAT_UH4( RTYPE, in0, in1, in2, in3, sat_val ) \
  1081. { \
  1082. SAT_UH2( RTYPE, in0, in1, sat_val ); \
  1083. SAT_UH2( RTYPE, in2, in3, sat_val ) \
  1084. }
  1085. #define SAT_UH4_UH( ... ) SAT_UH4( v8u16, __VA_ARGS__ )
  1086. /* Description : Saturate the halfword element values to the max
  1087. unsigned value of (sat_val+1 bits)
  1088. The element data width remains unchanged
  1089. Arguments : Inputs - in0, in1, sat_val
  1090. Outputs - in place operation
  1091. Return Type - as per RTYPE
  1092. Details : Each unsigned halfword element from 'in0' is saturated to the
  1093. value generated with (sat_val+1) bit range
  1094. The results are written in place
  1095. */
  1096. #define SAT_SH2( RTYPE, in0, in1, sat_val ) \
  1097. { \
  1098. in0 = ( RTYPE ) __msa_sat_s_h( ( v8i16 ) in0, sat_val ); \
  1099. in1 = ( RTYPE ) __msa_sat_s_h( ( v8i16 ) in1, sat_val ); \
  1100. }
  1101. #define SAT_SH2_SH( ... ) SAT_SH2( v8i16, __VA_ARGS__ )
  1102. #define SAT_SH4( RTYPE, in0, in1, in2, in3, sat_val ) \
  1103. { \
  1104. SAT_SH2( RTYPE, in0, in1, sat_val ); \
  1105. SAT_SH2( RTYPE, in2, in3, sat_val ); \
  1106. }
  1107. #define SAT_SH4_SH( ... ) SAT_SH4( v8i16, __VA_ARGS__ )
  1108. /* Description : Saturate the word element values to the max
  1109. unsigned value of (sat_val+1 bits)
  1110. The element data width remains unchanged
  1111. Arguments : Inputs - in0, in1, sat_val
  1112. Outputs - in place operation
  1113. Return Type - as per RTYPE
  1114. Details : Each unsigned word element from 'in0' is saturated to the
  1115. value generated with (sat_val+1) bit range
  1116. The results are written in place
  1117. */
  1118. #define SAT_SW2( RTYPE, in0, in1, sat_val ) \
  1119. { \
  1120. in0 = ( RTYPE ) __msa_sat_s_w( ( v4i32 ) in0, sat_val ); \
  1121. in1 = ( RTYPE ) __msa_sat_s_w( ( v4i32 ) in1, sat_val ); \
  1122. }
  1123. #define SAT_SW2_SW( ... ) SAT_SW2( v4i32, __VA_ARGS__ )
  1124. /* Description : Pack even byte elements of vector pairs
  1125. Arguments : Inputs - in0, in1, in2, in3
  1126. Outputs - out0, out1
  1127. Return Type - as per RTYPE
  1128. Details : Even byte elements of 'in0' are copied to the left half of
  1129. 'out0' & even byte elements of 'in1' are copied to the right
  1130. half of 'out0'.
  1131. */
  1132. #define PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1133. { \
  1134. out0 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  1135. out1 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
  1136. }
  1137. #define PCKEV_B2_SB( ... ) PCKEV_B2( v16i8, __VA_ARGS__ )
  1138. #define PCKEV_B2_UB( ... ) PCKEV_B2( v16u8, __VA_ARGS__ )
  1139. #define PCKEV_B2_SH( ... ) PCKEV_B2( v8i16, __VA_ARGS__ )
  1140. #define PCKEV_B2_SW( ... ) PCKEV_B2( v4i32, __VA_ARGS__ )
  1141. #define PCKEV_B3( RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2 ) \
  1142. { \
  1143. PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1144. out2 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in4, ( v16i8 ) in5 ); \
  1145. }
  1146. #define PCKEV_B3_UB( ... ) PCKEV_B3( v16u8, __VA_ARGS__ )
  1147. #define PCKEV_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1148. out0, out1, out2, out3 ) \
  1149. { \
  1150. PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1151. PCKEV_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1152. }
  1153. #define PCKEV_B4_SB( ... ) PCKEV_B4( v16i8, __VA_ARGS__ )
  1154. #define PCKEV_B4_UB( ... ) PCKEV_B4( v16u8, __VA_ARGS__ )
  1155. /* Description : Pack even halfword elements of vector pairs
  1156. Arguments : Inputs - in0, in1, in2, in3
  1157. Outputs - out0, out1
  1158. Return Type - as per RTYPE
  1159. Details : Even halfword elements of 'in0' are copied to the left half of
  1160. 'out0' & even halfword elements of 'in1' are copied to the
  1161. right half of 'out0'.
  1162. */
  1163. #define PCKEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1164. { \
  1165. out0 = ( RTYPE ) __msa_pckev_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  1166. out1 = ( RTYPE ) __msa_pckev_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
  1167. }
  1168. #define PCKEV_H2_SH( ... ) PCKEV_H2( v8i16, __VA_ARGS__ )
  1169. #define PCKEV_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1170. out0, out1, out2, out3 ) \
  1171. { \
  1172. PCKEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1173. PCKEV_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1174. }
  1175. #define PCKEV_H4_SH( ... ) PCKEV_H4( v8i16, __VA_ARGS__ )
  1176. /* Description : Pack even double word elements of vector pairs
  1177. Arguments : Inputs - in0, in1, in2, in3
  1178. Outputs - out0, out1
  1179. Return Type - as per RTYPE
  1180. Details : Even double elements of 'in0' are copied to the left half of
  1181. 'out0' & even double elements of 'in1' are copied to the right
  1182. half of 'out0'.
  1183. */
  1184. #define PCKEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1185. { \
  1186. out0 = ( RTYPE ) __msa_pckev_d( ( v2i64 ) in0, ( v2i64 ) in1 ); \
  1187. out1 = ( RTYPE ) __msa_pckev_d( ( v2i64 ) in2, ( v2i64 ) in3 ); \
  1188. }
  1189. #define PCKEV_D2_UB( ... ) PCKEV_D2( v16u8, __VA_ARGS__ )
  1190. #define PCKEV_D4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1191. out0, out1, out2, out3 ) \
  1192. { \
  1193. PCKEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1194. PCKEV_D2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1195. }
  1196. #define PCKEV_D4_UB( ... ) PCKEV_D4( v16u8, __VA_ARGS__ )
  1197. /* Description : Pack odd byte elements of vector pairs
  1198. Arguments : Inputs - in0, in1, in2, in3
  1199. Outputs - out0, out1
  1200. Return Type - as per RTYPE
  1201. Details : Odd byte elements of 'in0' are copied to the left half of
  1202. 'out0' & odd byte elements of 'in1' are copied to the right
  1203. half of 'out0'.
  1204. */
  1205. #define PCKOD_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1206. { \
  1207. out0 = ( RTYPE ) __msa_pckod_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
  1208. out1 = ( RTYPE ) __msa_pckod_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
  1209. }
  1210. #define PCKOD_B2_UB( ... ) PCKOD_B2( v16u8, __VA_ARGS__ )
  1211. #define PCKOD_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1212. out0, out1, out2, out3 ) \
  1213. { \
  1214. PCKOD_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1215. PCKOD_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1216. }
  1217. #define PCKOD_B4_UB( ... ) PCKOD_B4( v16u8, __VA_ARGS__ )
  1218. /* Description : Pack odd double word elements of vector pairs
  1219. Arguments : Inputs - in0, in1, in2, in3
  1220. Outputs - out0, out1
  1221. Return Type - as per RTYPE
  1222. Details : Odd double word elements of 'in0' are copied to the left half
  1223. of 'out0' & odd double word elements of 'in1' are copied to
  1224. the right half of 'out0'.
  1225. */
  1226. #define PCKOD_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1227. { \
  1228. out0 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) in0, ( v2i64 ) in1 ); \
  1229. out1 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) in2, ( v2i64 ) in3 ); \
  1230. }
  1231. #define PCKOD_D2_SH( ... ) PCKOD_D2( v8i16, __VA_ARGS__ )
  1232. #define PCKOD_D2_SD( ... ) PCKOD_D2( v2i64, __VA_ARGS__ )
  1233. /* Description : Each byte element is logically xor'ed with immediate 128
  1234. Arguments : Inputs - in0, in1
  1235. Outputs - in place operation
  1236. Return Type - as per RTYPE
  1237. Details : Each unsigned byte element from input vector 'in0' is
  1238. logically xor'ed with 128 and the result is stored in-place.
  1239. */
  1240. #define XORI_B2_128( RTYPE, in0, in1 ) \
  1241. { \
  1242. in0 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in0, 128 ); \
  1243. in1 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in1, 128 ); \
  1244. }
  1245. #define XORI_B2_128_UB( ... ) XORI_B2_128( v16u8, __VA_ARGS__ )
  1246. #define XORI_B2_128_SB( ... ) XORI_B2_128( v16i8, __VA_ARGS__ )
  1247. #define XORI_B3_128( RTYPE, in0, in1, in2 ) \
  1248. { \
  1249. XORI_B2_128( RTYPE, in0, in1 ); \
  1250. in2 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in2, 128 ); \
  1251. }
  1252. #define XORI_B3_128_SB( ... ) XORI_B3_128( v16i8, __VA_ARGS__ )
  1253. #define XORI_B4_128( RTYPE, in0, in1, in2, in3 ) \
  1254. { \
  1255. XORI_B2_128( RTYPE, in0, in1 ); \
  1256. XORI_B2_128( RTYPE, in2, in3 ); \
  1257. }
  1258. #define XORI_B4_128_UB( ... ) XORI_B4_128( v16u8, __VA_ARGS__ )
  1259. #define XORI_B4_128_SB( ... ) XORI_B4_128( v16i8, __VA_ARGS__ )
  1260. #define XORI_B5_128( RTYPE, in0, in1, in2, in3, in4 ) \
  1261. { \
  1262. XORI_B3_128( RTYPE, in0, in1, in2 ); \
  1263. XORI_B2_128( RTYPE, in3, in4 ); \
  1264. }
  1265. #define XORI_B5_128_SB( ... ) XORI_B5_128( v16i8, __VA_ARGS__ )
  1266. /* Description : Addition of signed halfword elements and signed saturation
  1267. Arguments : Inputs - in0, in1, in2, in3
  1268. Outputs - out0, out1
  1269. Return Type - as per RTYPE
  1270. Details : Signed halfword elements from 'in0' are added to signed
  1271. halfword elements of 'in1'. The result is then signed saturated
  1272. between halfword data type range
  1273. */
  1274. #define ADDS_SH2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
  1275. { \
  1276. out0 = ( RTYPE ) __msa_adds_s_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
  1277. out1 = ( RTYPE ) __msa_adds_s_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
  1278. }
  1279. #define ADDS_SH2_SH( ... ) ADDS_SH2( v8i16, __VA_ARGS__ )
  1280. #define ADDS_SH4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1281. out0, out1, out2, out3 ) \
  1282. { \
  1283. ADDS_SH2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
  1284. ADDS_SH2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
  1285. }
  1286. #define ADDS_SH4_UH( ... ) ADDS_SH4( v8u16, __VA_ARGS__ )
  1287. /* Description : Shift left all elements of vector (generic for all data types)
  1288. Arguments : Inputs - in0, in1, in2, in3, shift
  1289. Outputs - in place operation
  1290. Return Type - as per input vector RTYPE
  1291. Details : Each element of vector 'in0' is left shifted by 'shift' and
  1292. the result is written in-place.
  1293. */
  1294. #define SLLI_4V( in0, in1, in2, in3, shift ) \
  1295. { \
  1296. in0 = in0 << shift; \
  1297. in1 = in1 << shift; \
  1298. in2 = in2 << shift; \
  1299. in3 = in3 << shift; \
  1300. }
  1301. /* Description : Arithmetic shift right all elements of vector
  1302. (generic for all data types)
  1303. Arguments : Inputs - in0, in1, in2, in3, shift
  1304. Outputs - in place operation
  1305. Return Type - as per input vector RTYPE
  1306. Details : Each element of vector 'in0' is right shifted by 'shift' and
  1307. the result is written in-place. 'shift' is a GP variable.
  1308. */
  1309. #define SRA_4V( in0, in1, in2, in3, shift ) \
  1310. { \
  1311. in0 = in0 >> shift; \
  1312. in1 = in1 >> shift; \
  1313. in2 = in2 >> shift; \
  1314. in3 = in3 >> shift; \
  1315. }
  1316. /* Description : Shift right arithmetic rounded halfwords
  1317. Arguments : Inputs - in0, in1, shift
  1318. Outputs - in place operation
  1319. Return Type - as per RTYPE
  1320. Details : Each element of vector 'in0' is shifted right arithmetic by
  1321. number of bits respective element holds in vector 'shift'.
  1322. The last discarded bit is added to shifted value for rounding
  1323. and the result is written in-place.
  1324. 'shift' is a vector.
  1325. */
  1326. #define SRAR_H2( RTYPE, in0, in1, shift ) \
  1327. { \
  1328. in0 = ( RTYPE ) __msa_srar_h( ( v8i16 ) in0, ( v8i16 ) shift ); \
  1329. in1 = ( RTYPE ) __msa_srar_h( ( v8i16 ) in1, ( v8i16 ) shift ); \
  1330. }
  1331. #define SRAR_H2_SH( ... ) SRAR_H2( v8i16, __VA_ARGS__ )
  1332. #define SRAR_H4( RTYPE, in0, in1, in2, in3, shift ) \
  1333. { \
  1334. SRAR_H2( RTYPE, in0, in1, shift ) \
  1335. SRAR_H2( RTYPE, in2, in3, shift ) \
  1336. }
  1337. #define SRAR_H4_SH( ... ) SRAR_H4( v8i16, __VA_ARGS__ )
  1338. /* Description : Shift right logical all halfword elements of vector
  1339. Arguments : Inputs - in0, in1, in2, in3, shift
  1340. Outputs - in place operation
  1341. Return Type - as per RTYPE
  1342. Details : Each element of vector 'in0' is shifted right logical by
  1343. number of bits respective element holds in vector 'shift' and
  1344. the result is stored in-place.'shift' is a vector.
  1345. */
  1346. #define SRL_H4( RTYPE, in0, in1, in2, in3, shift ) \
  1347. { \
  1348. in0 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in0, ( v8i16 ) shift ); \
  1349. in1 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in1, ( v8i16 ) shift ); \
  1350. in2 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in2, ( v8i16 ) shift ); \
  1351. in3 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in3, ( v8i16 ) shift ); \
  1352. }
  1353. #define SRL_H4_UH( ... ) SRL_H4( v8u16, __VA_ARGS__ )
  1354. /* Description : Shift right arithmetic rounded (immediate)
  1355. Arguments : Inputs - in0, in1, shift
  1356. Outputs - in place operation
  1357. Return Type - as per RTYPE
  1358. Details : Each element of vector 'in0' is shifted right arithmetic by
  1359. value in 'shift'. The last discarded bit is added to shifted
  1360. value for rounding and the result is written in-place.
  1361. 'shift' is an immediate value.
  1362. */
  1363. #define SRARI_H2( RTYPE, in0, in1, shift ) \
  1364. { \
  1365. in0 = ( RTYPE ) __msa_srari_h( ( v8i16 ) in0, shift ); \
  1366. in1 = ( RTYPE ) __msa_srari_h( ( v8i16 ) in1, shift ); \
  1367. }
  1368. #define SRARI_H2_UH( ... ) SRARI_H2( v8u16, __VA_ARGS__ )
  1369. #define SRARI_H2_SH( ... ) SRARI_H2( v8i16, __VA_ARGS__ )
  1370. #define SRARI_H4( RTYPE, in0, in1, in2, in3, shift ) \
  1371. { \
  1372. SRARI_H2( RTYPE, in0, in1, shift ); \
  1373. SRARI_H2( RTYPE, in2, in3, shift ); \
  1374. }
  1375. #define SRARI_H4_UH( ... ) SRARI_H4( v8u16, __VA_ARGS__ )
  1376. #define SRARI_H4_SH( ... ) SRARI_H4( v8i16, __VA_ARGS__ )
  1377. #define SRARI_W2( RTYPE, in0, in1, shift ) \
  1378. { \
  1379. in0 = ( RTYPE ) __msa_srari_w( ( v4i32 ) in0, shift ); \
  1380. in1 = ( RTYPE ) __msa_srari_w( ( v4i32 ) in1, shift ); \
  1381. }
  1382. #define SRARI_W2_SW( ... ) SRARI_W2( v4i32, __VA_ARGS__ )
  1383. #define SRARI_W4( RTYPE, in0, in1, in2, in3, shift ) \
  1384. { \
  1385. SRARI_W2( RTYPE, in0, in1, shift ); \
  1386. SRARI_W2( RTYPE, in2, in3, shift ); \
  1387. }
  1388. #define SRARI_W4_SW( ... ) SRARI_W4( v4i32, __VA_ARGS__ )
  1389. /* Description : Multiplication of pairs of vectors
  1390. Arguments : Inputs - in0, in1, in2, in3
  1391. Outputs - out0, out1
  1392. Details : Each element from 'in0' is multiplied with elements from 'in1'
  1393. and the result is written to 'out0'
  1394. */
  1395. #define MUL2( in0, in1, in2, in3, out0, out1 ) \
  1396. { \
  1397. out0 = in0 * in1; \
  1398. out1 = in2 * in3; \
  1399. }
  1400. #define MUL4( in0, in1, in2, in3, in4, in5, in6, in7, \
  1401. out0, out1, out2, out3 ) \
  1402. { \
  1403. MUL2( in0, in1, in2, in3, out0, out1 ); \
  1404. MUL2( in4, in5, in6, in7, out2, out3 ); \
  1405. }
  1406. /* Description : Addition of 2 pairs of vectors
  1407. Arguments : Inputs - in0, in1, in2, in3
  1408. Outputs - out0, out1
  1409. Details : Each element in 'in0' is added to 'in1' and result is written
  1410. to 'out0'.
  1411. */
  1412. #define ADD2( in0, in1, in2, in3, out0, out1 ) \
  1413. { \
  1414. out0 = in0 + in1; \
  1415. out1 = in2 + in3; \
  1416. }
  1417. #define ADD4( in0, in1, in2, in3, in4, in5, in6, in7, \
  1418. out0, out1, out2, out3 ) \
  1419. { \
  1420. ADD2( in0, in1, in2, in3, out0, out1 ); \
  1421. ADD2( in4, in5, in6, in7, out2, out3 ); \
  1422. }
  1423. #define SUB4( in0, in1, in2, in3, in4, in5, in6, in7, \
  1424. out0, out1, out2, out3 ) \
  1425. { \
  1426. out0 = in0 - in1; \
  1427. out1 = in2 - in3; \
  1428. out2 = in4 - in5; \
  1429. out3 = in6 - in7; \
  1430. }
  1431. /* Description : Sign extend halfword elements from right half of the vector
  1432. Arguments : Input - in (halfword vector)
  1433. Output - out (sign extended word vector)
  1434. Return Type - signed word
  1435. Details : Sign bit of halfword elements from input vector 'in' is
  1436. extracted and interleaved with same vector 'in0' to generate
  1437. 4 word elements keeping sign intact
  1438. */
  1439. #define UNPCK_R_SH_SW( in, out ) \
  1440. { \
  1441. v8i16 sign_m; \
  1442. \
  1443. sign_m = __msa_clti_s_h( ( v8i16 ) in, 0 ); \
  1444. out = ( v4i32 ) __msa_ilvr_h( sign_m, ( v8i16 ) in ); \
  1445. }
  1446. /* Description : Zero extend unsigned byte elements to halfword elements
  1447. Arguments : Input - in (unsigned byte vector)
  1448. Outputs - out0, out1 (unsigned halfword vectors)
  1449. Return Type - signed halfword
  1450. Details : Zero extended right half of vector is returned in 'out0'
  1451. Zero extended left half of vector is returned in 'out1'
  1452. */
  1453. #define UNPCK_UB_SH( in, out0, out1 ) \
  1454. { \
  1455. v16i8 zero_m = { 0 }; \
  1456. \
  1457. ILVRL_B2_SH( zero_m, in, out0, out1 ); \
  1458. }
  1459. /* Description : Sign extend halfword elements from input vector and return
  1460. the result in pair of vectors
  1461. Arguments : Input - in (halfword vector)
  1462. Outputs - out0, out1 (sign extended word vectors)
  1463. Return Type - signed word
  1464. Details : Sign bit of halfword elements from input vector 'in' is
  1465. extracted and interleaved right with same vector 'in0' to
  1466. generate 4 signed word elements in 'out0'
  1467. Then interleaved left with same vector 'in0' to
  1468. generate 4 signed word elements in 'out1'
  1469. */
  1470. #define UNPCK_SH_SW( in, out0, out1 ) \
  1471. { \
  1472. v8i16 tmp_m; \
  1473. \
  1474. tmp_m = __msa_clti_s_h( ( v8i16 ) in, 0 ); \
  1475. ILVRL_H2_SW( tmp_m, in, out0, out1 ); \
  1476. }
  1477. /* Description : Butterfly of 4 input vectors
  1478. Arguments : Inputs - in0, in1, in2, in3
  1479. Outputs - out0, out1, out2, out3
  1480. Details : Butterfly operation
  1481. */
  1482. #define BUTTERFLY_4( in0, in1, in2, in3, out0, out1, out2, out3 ) \
  1483. { \
  1484. out0 = in0 + in3; \
  1485. out1 = in1 + in2; \
  1486. \
  1487. out2 = in1 - in2; \
  1488. out3 = in0 - in3; \
  1489. }
  1490. /* Description : Butterfly of 8 input vectors
  1491. Arguments : Inputs - in0 ... in7
  1492. Outputs - out0 .. out7
  1493. Details : Butterfly operation
  1494. */
  1495. #define BUTTERFLY_8( in0, in1, in2, in3, in4, in5, in6, in7, \
  1496. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  1497. { \
  1498. out0 = in0 + in7; \
  1499. out1 = in1 + in6; \
  1500. out2 = in2 + in5; \
  1501. out3 = in3 + in4; \
  1502. \
  1503. out4 = in3 - in4; \
  1504. out5 = in2 - in5; \
  1505. out6 = in1 - in6; \
  1506. out7 = in0 - in7; \
  1507. }
  1508. /* Description : Transpose input 8x8 byte block
  1509. Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
  1510. Outputs - out0, out1, out2, out3, out4, out5, out6, out7
  1511. Return Type - as per RTYPE
  1512. */
  1513. #define TRANSPOSE8x8_UB( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1514. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  1515. { \
  1516. v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
  1517. v16i8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
  1518. \
  1519. ILVR_B4_SB( in2, in0, in3, in1, in6, in4, in7, in5, \
  1520. tmp0_m, tmp1_m, tmp2_m, tmp3_m ); \
  1521. ILVRL_B2_SB( tmp1_m, tmp0_m, tmp4_m, tmp5_m ); \
  1522. ILVRL_B2_SB( tmp3_m, tmp2_m, tmp6_m, tmp7_m ); \
  1523. ILVRL_W2( RTYPE, tmp6_m, tmp4_m, out0, out2 ); \
  1524. ILVRL_W2( RTYPE, tmp7_m, tmp5_m, out4, out6 ); \
  1525. SLDI_B2_0( RTYPE, out0, out2, out1, out3, 8 ); \
  1526. SLDI_B2_0( RTYPE, out4, out6, out5, out7, 8 ); \
  1527. }
  1528. #define TRANSPOSE8x8_UB_UB( ... ) TRANSPOSE8x8_UB( v16u8, __VA_ARGS__ )
  1529. /* Description : Transpose 16x8 block into 8x16 with byte elements in vectors
  1530. Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7,
  1531. in8, in9, in10, in11, in12, in13, in14, in15
  1532. Outputs - out0, out1, out2, out3, out4, out5, out6, out7
  1533. Return Type - unsigned byte
  1534. */
  1535. #define TRANSPOSE16x8_UB_UB( in0, in1, in2, in3, in4, in5, in6, in7, \
  1536. in8, in9, in10, in11, in12, in13, in14, in15, \
  1537. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  1538. { \
  1539. v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
  1540. v16u8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
  1541. \
  1542. ILVEV_D2_UB( in0, in8, in1, in9, out7, out6 ); \
  1543. ILVEV_D2_UB( in2, in10, in3, in11, out5, out4 ); \
  1544. ILVEV_D2_UB( in4, in12, in5, in13, out3, out2 ); \
  1545. ILVEV_D2_UB( in6, in14, in7, in15, out1, out0 ); \
  1546. \
  1547. tmp0_m = ( v16u8 ) __msa_ilvev_b( ( v16i8 ) out6, ( v16i8 ) out7 ); \
  1548. tmp4_m = ( v16u8 ) __msa_ilvod_b( ( v16i8 ) out6, ( v16i8 ) out7 ); \
  1549. tmp1_m = ( v16u8 ) __msa_ilvev_b( ( v16i8 ) out4, ( v16i8 ) out5 ); \
  1550. tmp5_m = ( v16u8 ) __msa_ilvod_b( ( v16i8 ) out4, ( v16i8 ) out5 ); \
  1551. out5 = ( v16u8 ) __msa_ilvev_b( ( v16i8 ) out2, ( v16i8 ) out3 ); \
  1552. tmp6_m = ( v16u8 ) __msa_ilvod_b( ( v16i8 ) out2, ( v16i8 ) out3 ); \
  1553. out7 = ( v16u8 ) __msa_ilvev_b( ( v16i8 ) out0, ( v16i8 ) out1 ); \
  1554. tmp7_m = ( v16u8 ) __msa_ilvod_b( ( v16i8 ) out0, ( v16i8 ) out1 ); \
  1555. \
  1556. ILVEV_H2_UB( tmp0_m, tmp1_m, out5, out7, tmp2_m, tmp3_m ); \
  1557. out0 = ( v16u8 ) __msa_ilvev_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1558. out4 = ( v16u8 ) __msa_ilvod_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1559. \
  1560. tmp2_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) tmp1_m, ( v8i16 ) tmp0_m ); \
  1561. tmp3_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) out7, ( v8i16 ) out5 ); \
  1562. out2 = ( v16u8 ) __msa_ilvev_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1563. out6 = ( v16u8 ) __msa_ilvod_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1564. \
  1565. ILVEV_H2_UB( tmp4_m, tmp5_m, tmp6_m, tmp7_m, tmp2_m, tmp3_m ); \
  1566. out1 = ( v16u8 ) __msa_ilvev_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1567. out5 = ( v16u8 ) __msa_ilvod_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1568. \
  1569. tmp2_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) tmp5_m, ( v8i16 ) tmp4_m ); \
  1570. tmp2_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) tmp5_m, ( v8i16 ) tmp4_m ); \
  1571. tmp3_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) tmp7_m, ( v8i16 ) tmp6_m ); \
  1572. tmp3_m = ( v16u8 ) __msa_ilvod_h( ( v8i16 ) tmp7_m, ( v8i16 ) tmp6_m ); \
  1573. out3 = ( v16u8 ) __msa_ilvev_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1574. out7 = ( v16u8 ) __msa_ilvod_w( ( v4i32 ) tmp3_m, ( v4i32 ) tmp2_m ); \
  1575. }
  1576. /* Description : Transpose 4x4 block with half word elements in vectors
  1577. Arguments : Inputs - in0, in1, in2, in3
  1578. Outputs - out0, out1, out2, out3
  1579. Return Type - signed halfword
  1580. */
  1581. #define TRANSPOSE4x4_SH_SH( in0, in1, in2, in3, out0, out1, out2, out3 ) \
  1582. { \
  1583. v8i16 s0_m, s1_m; \
  1584. \
  1585. ILVR_H2_SH( in1, in0, in3, in2, s0_m, s1_m ); \
  1586. ILVRL_W2_SH( s1_m, s0_m, out0, out2 ); \
  1587. out1 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out0 ); \
  1588. out3 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out2 ); \
  1589. }
  1590. /* Description : Transpose 4x8 block with half word elements in vectors
  1591. Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
  1592. Outputs - out0, out1, out2, out3, out4, out5, out6, out7
  1593. Return Type - signed halfword
  1594. */
  1595. #define TRANSPOSE4X8_SH_SH( in0, in1, in2, in3, in4, in5, in6, in7, \
  1596. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  1597. { \
  1598. v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
  1599. v8i16 tmp0_n, tmp1_n, tmp2_n, tmp3_n; \
  1600. v8i16 zero_m = { 0 }; \
  1601. \
  1602. ILVR_H4_SH( in1, in0, in3, in2, in5, in4, in7, in6, \
  1603. tmp0_n, tmp1_n, tmp2_n, tmp3_n ); \
  1604. ILVRL_W2_SH( tmp1_n, tmp0_n, tmp0_m, tmp2_m ); \
  1605. ILVRL_W2_SH( tmp3_n, tmp2_n, tmp1_m, tmp3_m ); \
  1606. \
  1607. out0 = ( v8i16 ) __msa_ilvr_d( ( v2i64 ) tmp1_m, ( v2i64 ) tmp0_m ); \
  1608. out1 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) tmp1_m, ( v2i64 ) tmp0_m ); \
  1609. out2 = ( v8i16 ) __msa_ilvr_d( ( v2i64 ) tmp3_m, ( v2i64 ) tmp2_m ); \
  1610. out3 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) tmp3_m, ( v2i64 ) tmp2_m ); \
  1611. \
  1612. out4 = zero_m; \
  1613. out5 = zero_m; \
  1614. out6 = zero_m; \
  1615. out7 = zero_m; \
  1616. }
  1617. /* Description : Transpose 8x4 block with half word elements in vectors
  1618. Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
  1619. Outputs - out0, out1, out2, out3, out4, out5, out6, out7
  1620. Return Type - signed halfword
  1621. */
  1622. #define TRANSPOSE8X4_SH_SH( in0, in1, in2, in3, out0, out1, out2, out3 ) \
  1623. { \
  1624. v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
  1625. \
  1626. ILVR_H2_SH( in1, in0, in3, in2, tmp0_m, tmp1_m ); \
  1627. ILVL_H2_SH( in1, in0, in3, in2, tmp2_m, tmp3_m ); \
  1628. ILVR_W2_SH( tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out2 ); \
  1629. ILVL_W2_SH( tmp1_m, tmp0_m, tmp3_m, tmp2_m, out1, out3 ); \
  1630. }
  1631. /* Description : Transpose 8x8 block with half word elements in vectors
  1632. Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
  1633. Outputs - out0, out1, out2, out3, out4, out5, out6, out7
  1634. Return Type - as per RTYPE
  1635. */
  1636. #define TRANSPOSE8x8_H( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
  1637. out0, out1, out2, out3, out4, out5, out6, out7 ) \
  1638. { \
  1639. v8i16 s0_m, s1_m; \
  1640. v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
  1641. v8i16 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
  1642. \
  1643. ILVR_H2_SH( in6, in4, in7, in5, s0_m, s1_m ); \
  1644. ILVRL_H2_SH( s1_m, s0_m, tmp0_m, tmp1_m ); \
  1645. ILVL_H2_SH( in6, in4, in7, in5, s0_m, s1_m ); \
  1646. ILVRL_H2_SH( s1_m, s0_m, tmp2_m, tmp3_m ); \
  1647. ILVR_H2_SH( in2, in0, in3, in1, s0_m, s1_m ); \
  1648. ILVRL_H2_SH( s1_m, s0_m, tmp4_m, tmp5_m ); \
  1649. ILVL_H2_SH( in2, in0, in3, in1, s0_m, s1_m ); \
  1650. ILVRL_H2_SH( s1_m, s0_m, tmp6_m, tmp7_m ); \
  1651. PCKEV_D4( RTYPE, tmp0_m, tmp4_m, tmp1_m, tmp5_m, tmp2_m, tmp6_m, \
  1652. tmp3_m, tmp7_m, out0, out2, out4, out6 ); \
  1653. out1 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp0_m, ( v2i64 ) tmp4_m ); \
  1654. out3 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp1_m, ( v2i64 ) tmp5_m ); \
  1655. out5 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp2_m, ( v2i64 ) tmp6_m ); \
  1656. out7 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp3_m, ( v2i64 ) tmp7_m ); \
  1657. }
  1658. #define TRANSPOSE8x8_SH_SH( ... ) TRANSPOSE8x8_H( v8i16, __VA_ARGS__ )
  1659. /* Description : Transpose 4x4 block with word elements in vectors
  1660. Arguments : Inputs - in0, in1, in2, in3
  1661. Outputs - out0, out1, out2, out3
  1662. Return Type - signed word
  1663. */
  1664. #define TRANSPOSE4x4_SW_SW( in0, in1, in2, in3, out0, out1, out2, out3 ) \
  1665. { \
  1666. v4i32 s0_m, s1_m, s2_m, s3_m; \
  1667. \
  1668. ILVRL_W2_SW( in1, in0, s0_m, s1_m ); \
  1669. ILVRL_W2_SW( in3, in2, s2_m, s3_m ); \
  1670. \
  1671. out0 = ( v4i32 ) __msa_ilvr_d( ( v2i64 ) s2_m, ( v2i64 ) s0_m ); \
  1672. out1 = ( v4i32 ) __msa_ilvl_d( ( v2i64 ) s2_m, ( v2i64 ) s0_m ); \
  1673. out2 = ( v4i32 ) __msa_ilvr_d( ( v2i64 ) s3_m, ( v2i64 ) s1_m ); \
  1674. out3 = ( v4i32 ) __msa_ilvl_d( ( v2i64 ) s3_m, ( v2i64 ) s1_m ); \
  1675. }
  1676. /* Description : Add block 4x4
  1677. Arguments : Inputs - in0, in1, in2, in3, pdst, stride
  1678. Details : Least significant 4 bytes from each input vector are added to
  1679. the destination bytes, clipped between 0-255 and stored.
  1680. */
  1681. #define ADDBLK_ST4x4_UB( in0, in1, in2, in3, p_dst, stride ) \
  1682. { \
  1683. uint32_t src0_m, src1_m, src2_m, src3_m; \
  1684. uint32_t out0_m, out1_m, out2_m, out3_m; \
  1685. v8i16 inp0_m, inp1_m, res0_m, res1_m; \
  1686. v16i8 dst0_m = { 0 }; \
  1687. v16i8 dst1_m = { 0 }; \
  1688. v16i8 zero_m = { 0 }; \
  1689. \
  1690. ILVR_D2_SH( in1, in0, in3, in2, inp0_m, inp1_m ) \
  1691. LW4( p_dst, stride, src0_m, src1_m, src2_m, src3_m ); \
  1692. INSERT_W2_SB( src0_m, src1_m, dst0_m ); \
  1693. INSERT_W2_SB( src2_m, src3_m, dst1_m ); \
  1694. ILVR_B2_SH( zero_m, dst0_m, zero_m, dst1_m, res0_m, res1_m ); \
  1695. ADD2( res0_m, inp0_m, res1_m, inp1_m, res0_m, res1_m ); \
  1696. CLIP_SH2_0_255( res0_m, res1_m ); \
  1697. PCKEV_B2_SB( res0_m, res0_m, res1_m, res1_m, dst0_m, dst1_m ); \
  1698. \
  1699. out0_m = __msa_copy_u_w( ( v4i32 ) dst0_m, 0 ); \
  1700. out1_m = __msa_copy_u_w( ( v4i32 ) dst0_m, 1 ); \
  1701. out2_m = __msa_copy_u_w( ( v4i32 ) dst1_m, 0 ); \
  1702. out3_m = __msa_copy_u_w( ( v4i32 ) dst1_m, 1 ); \
  1703. SW4( out0_m, out1_m, out2_m, out3_m, p_dst, stride ); \
  1704. }
  1705. /* Description : Dot product and addition of 3 signed halfword input vectors
  1706. Arguments : Inputs - in0, in1, in2, coeff0, coeff1, coeff2
  1707. Output - out0_m
  1708. Return Type - signed halfword
  1709. Details : Dot product of 'in0' with 'coeff0'
  1710. Dot product of 'in1' with 'coeff1'
  1711. Dot product of 'in2' with 'coeff2'
  1712. Addition of all the 3 vector results
  1713. out0_m = (in0 * coeff0) + (in1 * coeff1) + (in2 * coeff2)
  1714. */
  1715. #define DPADD_SH3_SH( in0, in1, in2, coeff0, coeff1, coeff2 ) \
  1716. ( { \
  1717. v8i16 tmp1_m; \
  1718. v8i16 out0_m; \
  1719. \
  1720. out0_m = __msa_dotp_s_h( ( v16i8 ) in0, ( v16i8 ) coeff0 ); \
  1721. out0_m = __msa_dpadd_s_h( out0_m, ( v16i8 ) in1, ( v16i8 ) coeff1 ); \
  1722. tmp1_m = __msa_dotp_s_h( ( v16i8 ) in2, ( v16i8 ) coeff2 ); \
  1723. out0_m = __msa_adds_s_h( out0_m, tmp1_m ); \
  1724. \
  1725. out0_m; \
  1726. } )
  1727. /* Description : Pack even elements of input vectors & xor with 128
  1728. Arguments : Inputs - in0, in1
  1729. Output - out_m
  1730. Return Type - unsigned byte
  1731. Details : Signed byte even elements from 'in0' and 'in1' are packed
  1732. together in one vector and the resulting vector is xor'ed with
  1733. 128 to shift the range from signed to unsigned byte
  1734. */
  1735. #define PCKEV_XORI128_UB( in0, in1 ) \
  1736. ( { \
  1737. v16u8 out_m; \
  1738. out_m = ( v16u8 ) __msa_pckev_b( ( v16i8 ) in1, ( v16i8 ) in0 ); \
  1739. out_m = ( v16u8 ) __msa_xori_b( ( v16u8 ) out_m, 128 ); \
  1740. out_m; \
  1741. } )
  1742. /* Description : Pack even byte elements, extract 0 & 2 index words from pair
  1743. of results and store 4 words in destination memory as per
  1744. stride
  1745. Arguments : Inputs - in0, in1, in2, in3, pdst, stride
  1746. */
  1747. #define PCKEV_ST4x4_UB( in0, in1, in2, in3, p_dst, stride ) \
  1748. { \
  1749. uint32_t out0_m, out1_m, out2_m, out3_m; \
  1750. v16i8 tmp0_m, tmp1_m; \
  1751. \
  1752. PCKEV_B2_SB( in1, in0, in3, in2, tmp0_m, tmp1_m ); \
  1753. \
  1754. out0_m = __msa_copy_u_w( ( v4i32 ) tmp0_m, 0 ); \
  1755. out1_m = __msa_copy_u_w( ( v4i32 ) tmp0_m, 2 ); \
  1756. out2_m = __msa_copy_u_w( ( v4i32 ) tmp1_m, 0 ); \
  1757. out3_m = __msa_copy_u_w( ( v4i32 ) tmp1_m, 2 ); \
  1758. \
  1759. SW4( out0_m, out1_m, out2_m, out3_m, p_dst, stride ); \
  1760. }
  1761. /* Description : Pack even byte elements and store byte vector in destination
  1762. memory
  1763. Arguments : Inputs - in0, in1, pdst
  1764. */
  1765. #define PCKEV_ST_SB( in0, in1, p_dst ) \
  1766. { \
  1767. v16i8 tmp_m; \
  1768. tmp_m = __msa_pckev_b( ( v16i8 ) in1, ( v16i8 ) in0 ); \
  1769. ST_SB( tmp_m, ( p_dst ) ); \
  1770. }
  1771. #define AVC_CALC_DPADD_H_6PIX_2COEFF_SH( in0, in1, in2, in3, in4, in5 ) \
  1772. ( { \
  1773. v4i32 tmp0_m, tmp1_m; \
  1774. v8i16 out0_m, out1_m, out2_m, out3_m; \
  1775. v8i16 minus5h_m = __msa_ldi_h( -5 ); \
  1776. v8i16 plus20h_m = __msa_ldi_h( 20 ); \
  1777. \
  1778. ILVRL_H2_SW( in5, in0, tmp0_m, tmp1_m ); \
  1779. \
  1780. tmp0_m = __msa_hadd_s_w( ( v8i16 ) tmp0_m, ( v8i16 ) tmp0_m ); \
  1781. tmp1_m = __msa_hadd_s_w( ( v8i16 ) tmp1_m, ( v8i16 ) tmp1_m ); \
  1782. \
  1783. ILVRL_H2_SH( in1, in4, out0_m, out1_m ); \
  1784. DPADD_SH2_SW( out0_m, out1_m, minus5h_m, minus5h_m, tmp0_m, tmp1_m ); \
  1785. ILVRL_H2_SH( in2, in3, out2_m, out3_m ); \
  1786. DPADD_SH2_SW( out2_m, out3_m, plus20h_m, plus20h_m, tmp0_m, tmp1_m ); \
  1787. \
  1788. SRARI_W2_SW( tmp0_m, tmp1_m, 10 ); \
  1789. SAT_SW2_SW( tmp0_m, tmp1_m, 7 ); \
  1790. out0_m = __msa_pckev_h( ( v8i16 ) tmp1_m, ( v8i16 ) tmp0_m ); \
  1791. \
  1792. out0_m; \
  1793. } )
  1794. #define AVC_HORZ_FILTER_SH( in, mask0, mask1, mask2 ) \
  1795. ( { \
  1796. v8i16 out0_m, out1_m; \
  1797. v16i8 tmp0_m, tmp1_m; \
  1798. v16i8 minus5b = __msa_ldi_b( -5 ); \
  1799. v16i8 plus20b = __msa_ldi_b( 20 ); \
  1800. \
  1801. tmp0_m = __msa_vshf_b( ( v16i8 ) mask0, in, in ); \
  1802. out0_m = __msa_hadd_s_h( tmp0_m, tmp0_m ); \
  1803. \
  1804. tmp0_m = __msa_vshf_b( ( v16i8 ) mask1, in, in ); \
  1805. out0_m = __msa_dpadd_s_h( out0_m, minus5b, tmp0_m ); \
  1806. \
  1807. tmp1_m = __msa_vshf_b( ( v16i8 ) ( mask2 ), in, in ); \
  1808. out1_m = __msa_dpadd_s_h( out0_m, plus20b, tmp1_m ); \
  1809. \
  1810. out1_m; \
  1811. } )
  1812. #endif /* X264_MIPS_MACROS_H */